Reversible circuits with testability using quantum controlled NOT and swap gates

Abstract

A new method of designing reversible circuits with inbuilt testability is presented by exploiting the properties of quantum controlled NOT and Swap gates. The design process is based on the methodology of placement of gates in such a manner that it produces parity preserving circuits. The testability of these circuits can be achieved by comparing the input and output parity under single bit fault detection. Experiments are conducted on a set of benchmark circuits which show an average reduction up to 51% in operating costs, when compared to existing work.