Load Based Dynamic Priority Arbiter for NoC Architecture

Abstract

The evolution of Very Large Scale Integration (VLSI) and the semiconductor industry have led to the focus on multicore architectures. Network on Chip (NoC) is one of such arrangement which is an interconnection framework comprised of cores, routers, and links. The output port for each request from the input port must be computed, and the output channel must be reserved for the next router. However, the same output port can be requested by more than one input port, but only one request can be granted at a time. Multiple requests for a single output channel will lead to congestion of the packets, thereby increasing the network latency and leading to packet losses. The arbiter selects any one of the input ports and grants permission to use the requested output port while putting the other input port requests to wait. For a congestion-free traversal of packets and to avoid dropping of packets, a Load based Dynamic Priority Arbiter (LDPA) with dynamically changing priorities during run time based on the input port load has been proposed. The proposed customized arbiter LDPA works based on the updates made in the reservations of each input port. The priority of each input port is given according to the average load. More weight is allotted to the highly loaded input ports. By randomization, the chance is given to the lower priority input ports to reduce starvation and hence latency. With the use of the proposed LDPA, the average network latency is reduced by about 15.98% when compared to that of baseline FIFO arbiter, without any compromise in power and throughput.